1. Field of the Invention
The present invention relates generally to apparatus for protecting circuits from Electro Static Discharge (ESD) and, in particular, a snapback circuit capable of being triggered at low voltages.
2. Description of Related Art
An integrated circuit may be subjected to an ESD event that can damage or destroy circuitry of the integrated circuit. Various types of ESD clamps have been devised which are typically connected in parallel to the circuitry to be protected and operate to shunt current around the circuitry to be protected during an ESD event. In order to provide effective protection while not interfering with the normal operation of the integrated circuit, the design of the ESD clamp must, among other things, take into account the breakdown voltage of the circuit to be protected and the normal operating voltage of the circuit. Normal operating voltages should not be sufficient to trigger the ESD clamp. Further, after the occurrence of an ESD event, the protection circuit should disengage, that is, unlatch, once normal operating voltages return. Recent developments in the design of integrated circuits, including reduced power supply voltages, increased operating frequencies, smaller device geometries and smaller breakdown voltages have made the design of effective ESD clamp and other protection circuits more difficult.
FIG. 1 shows a curve 10 that represents the voltage-current (V-I) characteristics of a typical ESD clamp circuit, sometimes referred to as a snapback clamp. Curves 12 and 14 which represent the characteristics of two typical devices to be protected. The primary objective of the ESD clamp circuit is to rapidly respond to an ESD event by shunting the large current (typically a few amperes) away from the circuit to be protected so that any voltages generated in the circuit to be protected are sufficiently small to avoid damage or destruction of the circuit. Further, the ESD clamp circuit must not be triggered during normal operation and should unclamp at the end of the event so that normal operation can resume, as previously noted.
Referring to FIG. 1, an ESD event will cause the voltage across the clamp circuit and protected circuit to rapidly increase. The ESD event will produce a current having a magnitude of IESD, which, as previously noted can be as large as a few amperes. As the voltage across the clamp and the circuit increases, the claim will start to turn on significantly, that is trigger, at point 10A of curve 10. The typical clamp will then enter a negative resistance area of operation and will continue conducting an increasing current until the voltage across the clamp has been reduced to a holding voltage indicated by point 10B. The clamp current will ideally continue to increase until the current reaches the maximum current IESD at point 10C. If the maximum IESD current is too large for the clamp, the clamp will eventually reach a breakdown voltage at point 10D, with any additional current causing the clamp to be damaged or destroyed.
Assuming that the circuit to be protected represented by curve 12 is subjected to the same ESD event, without the presence of the clamp circuit, the circuit to be protected would begin conducting current as indicated by point 12A of the curve. The circuit would continue to conduct current until it suffered a voltage break down at point 12B, with the increasing ESD current causing the circuit to be destroyed. However, assuming that the ESD clamp is in place, the clamp will be triggered at a voltage at point 10A that is lower than the voltage at point 12A of the circuit to be protected. Thus, the ESD clamp will prevent the circuit to be protected from being exposed to a voltage sufficiently high to cause the circuit to break down and will cause all of the ESD current to be bypassed through the clamp.
The alternative circuit to be protected, having I-V characteristics represented by curve 14, will start to breakdown at point 14A. Since the voltage at point 14A is lower than the trigger voltage of the ESD clamp at point 10A, the clamp will not turn on during the event. As a result, the clamp will not be capable of protecting the circuit from the ESD event.
Although there are a wide variety of circuits that can be used as ESD clamps, silicon controlled rectifiers (SCR) are frequently used for this application. FIGS. 2A and 2B depict one conventional implementation of an SCR type clamp circuit commonly used in ESD application. The FIG. 2A, 2B structure is sometimes called a low voltage triggered silicon controlled rectifier (LVTSCR). The exemplary LVTSCR is formed in a P type substrate 18. An N well 20 is formed in the substrate 18, with an N+ region 22 forming a contact to the N well. A P+ region 24 also formed in the N well 20, is separated from the N+ region by a shallow trench isolation (sti) region 26A. An N+ extension 20A is formed near one end of the N well 20 and is separated from P+ region 24 by a further shallow trench isolation region 26B. Respective N+ and P+ regions 22 and 24 are electrically interconnected by a metal track 28, with this connection forming the anode terminal of the LTVSCR. As can best be seen in FIG. 2B, metal track 28 is electrically connected to N+ region 22 and P+ region 24 by way of a plurality of respective contact openings 22A and 24A formed in the oxide layer (not designated) disposed over those regions.
A further N+ region 30 is formed in the P substrate 18 and spaced apart from the extension 20A so as to form a channel region 18A intermediate the N+ regions 30 and 20A. A polysilicon gate 32 is disposed over the channel region 18A and separated from the channel regions by a thin gate oxide (not designated). A P+ region 34 is formed in the P substrate 18 and separated from region 30 by a shallow trench isolation region 26C, with P+ region 34 forming a contact with the P substrate 18. P+ region 34 and N+ region 30 are connected together by a metal track 36 which forms the cathode of the LVTSCR 16. Again as can best be seen in FIG. 2B, metal track 36 is electrically connected to N+ region 30 and P+ region 34 by way of a plurality of respective contact openings 30A and 34A formed in the oxide layer (not designated) disposed over those regions.
LVTSCR 16, as is the case for all SCR type structures, can be viewed as a PNP transistor combined with an NPN transistor, with the base of the PNP transistor and the collector of the PNP transistor being common and the collector of the PNP and the base of the NPN being common. P+ region 24, N well 20 and P substrate 18 form the respective emitter, base and collector regions of the PNP device. The N well region 20 further defines a resistor having one terminal which is part of the base on the PNP and a second terminal which is connected to the emitter by way of N+ region 22 and metal track 28. The NPN device includes the N+ region 30, the P substrate 18 and the N well 20 which form the emitter, base and collector of the device. A resistor is formed in the P substrate 18 having one terminal that is part of the NPN base region and a second terminal connected to the emitter by way of P+ region 34 and metal track 36.
In operation, at the beginning of and ESD event, when the voltage is low, the PN junction between N well 20 and the P substrate 18 is slightly reversed biased. This reversed biased PN junction forms the common base-collector junction of the NPN and PNP devices. As the voltage increases, the leakage current increases when the PN junction begins avalanching. The junction voltage at which avalanching occurs is reduced by the highly doped N+ region 20A. The leakage current flow through the N well 20 resistor disposed between the base and emitter of the PNP thereby tending to turn on the PNP device. The current is enhanced by the nMOS transistor formed by drain region 20A, sometimes referred to as a floating drain, and source region 30. This nMOS transistor, which is effectively connected in parallel with the NPN transistor, will produce an added current though the N well resistor 20 thereby adding to the current that turns on the PNP transistor. The LVTSCR turn on voltage or trigger voltage is represented by point 10A of FIG. 1.
Eventually, the increase in current in the PNP and NPN transistors will increase the current gain of the two devices so that each device will cause the other device to turn on. This regenerative SCR action will continue thereby reducing the voltage across the LVTSCR until the voltage drops to a holding voltage represented by point 10B of FIG. 1. As additional ESD current is conducted, the voltage across the LVTSCR will increase until the total IESD current is shunted through the device, as shown by point 10C of FIG. 1. Ideally, the device has sufficient current conduction capability so that the voltage never reaches the thermal breakdown voltage represented by point 10D.
The threshold voltage of the LVTSCR can be adjusted by various means, including controlling the gate-source voltage of the nMOS transistor. Gate 32 could by grounded thereby producing a relatively high threshold voltage. A resistive divider can also be used to bias the gate voltage. Further, an RC network can be used, with a capacitor of suitable size connected between the gate 32 and anode 28 and a resistor of suitable size being connected between the gate 32 and the cathode 36.
Although prior art ESD protection circuits, such as the LVTSCR 16 of FIGS. 2A and 2B provide adequate circuit protection in many applications, the required capabilities of such circuits have increase greatly with recent developments in newer integrated circuit designs.